acStratumLineTimingPortSlot2

  • 1.3.6.1.4.1.2785.2.9.1.1.15
  • Access readwrite
  • Type Unknown
  • Default 1

When configured for line timing, this value describes which port on the SONET card will be used to drive the line. This value is not applicable when not configured for line timing.

Table columns

17 objects
Oid Name Access Type
1.3.6.1.4.1.2785.2.9.1.1.1 acStratumNodeId notifyonly AcNodeId
1.3.6.1.4.1.2785.2.9.1.1.2 acStratumClockSource readwrite internal(1), bits(2), line(3)
1.3.6.1.4.1.2785.2.9.1.1.3 acStratumOpStatusModuleA readonly AcOpStatus
1.3.6.1.4.1.2785.2.9.1.1.4 acStratumOpStatusModuleB readonly AcOpStatus
1.3.6.1.4.1.2785.2.9.1.1.5 acStratumAlarmStatusModuleA readonly Unknown
1.3.6.1.4.1.2785.2.9.1.1.6 acStratumAlarmStatusModuleB readonly Unknown
1.3.6.1.4.1.2785.2.9.1.1.7 acStratumCurrentClockSourceModuleA readonly unknown(0), none(1), bits-a(2), bits-b(3), line-slot1-port1(4), line-slot1-port2(5), line-slot2-port1(6), line-slot2-port2(7), holdover(8), internal(9)
1.3.6.1.4.1.2785.2.9.1.1.8 acStratumCurrentClockSourceModuleB readonly unknown(0), none(1), bits-a(2), bits-b(3), line-slot1-port1(4), line-slot1-port2(5), line-slot2-port1(6), line-slot2-port2(7), holdover(8), internal(9)
1.3.6.1.4.1.2785.2.9.1.1.9 acStratumLockoutReference readwrite Unknown
1.3.6.1.4.1.2785.2.9.1.1.10 acStratumManualSwitch readwrite none(0), bits-a(1), bits-b(2), line-slot1(3), line-slot2(4)
1.3.6.1.4.1.2785.2.9.1.1.11 acStratumForcedSwitch readwrite none(0), bits-a(1), bits-b(2), line-slot1(3), line-slot2(4)
1.3.6.1.4.1.2785.2.9.1.1.12 acStratumRevertiveRefSwitchEnabled readwrite TruthValue
1.3.6.1.4.1.2785.2.9.1.1.13 acStratumClearAlarms readwrite TruthValue
1.3.6.1.4.1.2785.2.9.1.1.14 acStratumLineTimingPortSlot1 readwrite Unknown
1.3.6.1.4.1.2785.2.9.1.1.15 acStratumLineTimingPortSlot2 readwrite Unknown
1.3.6.1.4.1.2785.2.9.1.1.16 acStratumBITSFramingType readwrite esf(1), d4(2)
1.3.6.1.4.1.2785.2.9.1.1.17 acStratumCurrentClockSourceSystem readonly unknown(0), bits-a(1), bits-b(2), line-slot1-port1(3), line-slot1-port2(4), line-slot2-port1(5), line-slot2-port2(6), holdover-clock-a(7), holdover-clock-b(8), internal-clock-a(9), internal-clock-b(10), internal-sonet-slot1(11), internal-sonet-slot2(12)

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